Differential signaling is commonly used for communication of data between multiple integrated circuits mounted to a common printed circuit board, and between integrated circuits mounted to separate printed circuit boards coupled to a common backplane. A transmission line formed on the printed circuit board or backplane serves as the data communication interface.
Differential signals carried by the transmission line exhibit multiple transmission modes, for example even and odd modes of signal propagation. As transmission rates increase, these modes become higher order. As a result, the adverse effects of reflection and crosstalk begin to affect signal transmission. It is a common objective in such data communication systems to be able to drive and receive the data signals at high transmission rates, while minimizing reflected energy in the system and minimizing crosstalk between signals of neighboring transmission lines.
The present invention relates to a low-voltage transmitter and receiver adapted for differential signaling via transmission lines between integrated circuits at very-high data exchange rates. Such transmission is achieved in a manner that minimizes reflected energy and minimizes crosstalk between signals propagating over neighboring transmission lines.
In achieving optimal transmission characteristics, a bridge circuit is employed to drive the signal. The bridge circuit is connected in series between a pull-up and pull-down resistance, the resistance values being programmable to maintain optimal communication rates and quality.
The pull-up and pull-down resistors preferably comprise a bank of transistors having source-to-drain resistance values that are binary multiples of each other. The transistors are preferably coupled in parallel with each other and in parallel with a resistor, such that the transistors can be selectively activated by a binary voltage-control data word. By activating different transistors in the network, different overall resistance values can be achieved.
A receiver resistor is applied at the receiver end of the communication channel between the first and second differential signal components, across the inputs to a receiver comparator which converts the received differential signal to a standard binary signal at a voltage compatible with the system voltage. The receiver resistor preferably also comprises a programmable resistor network, as described above.
In a first embodiment, the present invention comprises a differential data communication system. The system comprises a differential driver for generating a differential data signal from a binary data signal, the differential data signal being adapted for transmission over a communication medium. A pull-up resistor is coupled between the differential driver and a first voltage source for controlling an upper voltage level of the differential data signal. A pull-down resistor is coupled between the differential driver and a second voltage source for controlling a lower voltage level of the differential data signal. The pull-up and pull-down resistors have variable resistance values that are programmable for maintaining the upper and lower voltage levels for optimal data transmission of the differential data signal by the differential driver over the communication medium.
In a preferred embodiment, the first voltage source comprises a supply voltage, and the second voltage source comprises a ground voltage.
The pull-up and pull-down resistors each preferably comprise a plurality of transistors in parallel between first and second resistor terminals, the transistors being of different sizes such that their respective source-to-drain resistance values are different when activated. A parallel resistor is preferably coupled in parallel with the plurality of transistors. The respective source-to-drain resistance values of the transistors are preferably substantially binary multiples of each other. The transistors are preferably activated by a binary selection signal, the bits of which are coupled to respective gates of the transistors. The binary selection signal can be determined by a calibration circuit.
The system may further comprise a receiver comprising a differential comparator and a receiver resistor coupled between first and second inputs to the comparator, the receiver being coupled to the communication medium for receiving the differential data signal and for converting the differential data signal to a binary data signal. The receiver resistor preferably comprises a plurality of transistors in parallel between first and second resistor terminals, the transistors being of different sizes such that their respective source-to-drain resistance values are different when activated, a plurality of first bidirectional series resistors between each transistor and the first resistor terminal, and a plurality of second bidirectional resistors between each transistor and the second resistor terminal. A parallel resistor may be coupled in parallel with the plurality of transistors. The respective source-to-drain resistance values of the transistors are preferably substantially binary multiples of each other. The transistors may be activated by a binary selection signal, the bits of which are coupled to respective gates of the transistors. The binary selection signal may be determined by a calibration circuit.
To further achieve optimal transmission characteristics, a calibration circuit and method are provided. The calibration system is formed on the same integrated circuit as the differential driver and receiver pair, and includes a clone of the programmable resistor networks used by the driver and receiver. Accordingly, control values for the resistor networks can be determined and continually updated during operation of the device, while minimizing the effects of variability in fabrication of the devices, supply voltage, and operating temperature.
By integrating transmitter and receiver resistors on a common chip, package parasitic inductance and capacitance effects are avoided that would otherwise introduce distortion and reflection into the signal.
In this manner, a double-terminated transmission medium is realized, having a transmitter output impedance and a receiver output impedance equal to the differential impedance Z0 of the transmission line.
In a second embodiment, the present invention is directed to a calibration circuit for a differential data communication system including a differential driver having a variable pull-up resistor and pull-down resistor and a differential receiver having a variable receive termination resistor. The calibration circuit includes a calibration pull-up resistor and a calibration pull-down resistor in series between a first and second voltage source. A calibration receive termination resistor is in series between the calibration pull-up and pull down resistors. Each of the calibration pull-up and pull-down resistors and the calibration receive termination resistor comprise a bank of calibration transistors in parallel with each other, the calibration transistors of a common bank being of different sizes such that their respective source-to-drain values are different when activated. The calibration transistors are selectively activated by binary selection signals, the bits of which are applied to the respective gates of the transistors. The calibration receive termination resistor further includes bidirectional series resistors in series with the calibration transistors of that bank. An optimizing circuit determines optimal binary selection signals for the calibration pull-up resistor, calibration pull-down resistor, and calibration receive termination resistor.
The differential driver, differential receiver, and calibration circuit all preferably reside on a common integrated circuit. A series resistor bank may be provided between the first and second voltage sources for providing first and second reference voltages, the first and second fixed reference voltages in turn being provided to one of the positive and negative inputs of first and second respective comparators. In this case, a first variable reference voltage may be provided at the interface of the calibration pull-up resistor and a first terminal of the calibration receive termination resistor, and a second variable reference voltage may be provided at the interface of the calibration pull-down resistor and a second terminal of the calibration receive termination resistor, the first and second variable reference voltages being provided to the other of the positive and negative inputs of the first and second comparators.
The binary selection signals of the calibration pull-up transistor, calibration pull-down transistor, and calibration receive termination resistor are preferably optimized by applying the binary selection signals to the respective transistor banks, and by monitoring the comparator outputs, such that the first and second variable reference voltages substantially match the first and second fixed reference voltages. The binary selection signals are preferably adjusted incrementally, during optimization, based on the comparator outputs, for example, by increments of a single binary bit.